Design of Generic Channels ( 2 Channels Implementation)
DMA Controller( Multiple DMAs with Arbiter Resource Sharing).
Device To Be Targeted – Xilinx Spartan 3 FPGA (xc3s200-4ft-256).
1) Platform Flash Ram to support the back
up for FPGA.
2) 2 SRAMs (Asynchronous) of 256K *16
each for coded and decoded DATA.
3) RS232, VGA, PS2 Communication Ports.
Languages To Be USED – VHDL or Verilog.
Xilinx 8.2i, Leonardo Spectrum 5.1,
Modelsim 5.1 PE.
Tenure Approximated – 4 Months.
Complete Step by Step Design Process to be Followed —
1. SRS — System Requirement Specification.
2. Design Partioning.
3. HDL Behavioral Coding.
4. Functional Verification.
5. RTL Coding.
6. Design Synthesis.
7. Timing Simulation.
8. Static Time Analysis.
9. Dynamic Time Analysis.
10. Timing and Area and Pin Constraints.
11. Translating the design in Libraries.
12. Mapping of Design.
13. Placement of Cells and Routing the Signals (PAR).
14. Programming File Generation.
15. JTAG (Joint Test Action Group) Configuration.
16. Burning the Device.
17. H/W Verification.
This design will facilitate many DMAs (Each bi – channel) to share a common Memory of 2 MB size via an Arbiter. The DMAs, I/Os, Arbiter, Memory will be designed and coded in VHDL/Verilog. Test benches for all will be designed. The wrapper will be created as an integration of the design The Test bench for the wrapper will be designed. Finally the design will be implemented and verified.